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JSC and Partners to Build JURECA Booster Module

JSC, Intel, ParTec and Dell have partnered up to develop and deploy a "Booster" component for the JURECA system. Following the successful pioneering work in the EU-funded DEEP and DEEP-ER projects (see current press release at, the combined Cluster-Booster JURECA system will enable users to dynamically distribute their applications between multi- and many-core modules to optimally leverage their respective advantages for the execution of sub-portions of their application. The Booster will be built from Intel Xeon Phi 7250-F (Knights Landing) processors with on-package Intel Omni-Path Architecture interfaces. It was co-designed by Intel and JSC to enable maximum scalability for large-scale simulations and will have a peak performance of 5 PFLOP/s. The system will be supplied by Intel with its subcontractor Dell.

The JURECA Booster will be directly connected to the JURECA cluster, a system delivered by T-Platforms in 2015. As part of the project, a novel high-speed bridging mechanism between JURECA’s InfiniBand EDR and the Booster’s Intel Omni-Path Architecture interconnect will be developed by the group of partners. The Cluster and Booster modules will be operated as a single system although users will continue to be able to choose to execute on a subset of the modular system as required for their research.

The system installation is planned for late autumn 2017. The computing time on the system will be made available to members of Forschungszentrum Jülich and RWTH Aachen University through JARA-HPC/VSR calls. Moreover, during a two-year interim period scientists at German universities and research institutions can request computing time via the John von Neumann Institute of Compute (NIC) calls.
(Contact: Dr. Dorian Krause,

JSC News No. 250, 7 June 2017









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