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PADC Annual Workshop 2018

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11 Apr 2018 09:00
end
12 Apr 2018 15:00
venue
Jülich Supercomputing Centre, Rotunda, building 16.4, room 301
Contents:

IBM, JSC and NVIDIA have jointly set-up the “POWER Acceleration and Design Center” (PADC) to enable applications for architectures based on OpenPOWER technologies and to facilitate R&D in the context of such technologies and architectures. The workshop will allow to show-case results of these efforts. Furthermore, several hands-on training sessions on advanced technologies and approaches in the following areas are planned

  • Deep Learning and HPC
  • Compiler and programming models
  • Accelerating applications using CAPI-attached FPGAs
  • Interfacing with non-volatile memory
Agenda:
see Indico-Server
Date:
Wednesday, 11 April 2018, 09:00, until
Thursday, 12 April 2018, 15:00
Venue:
Jülich Supercomputing Centre, room 301, building 16.4 (Rotunde)
Registration:
Interested scientists are cordially invited to participate. The number of participants is limited and we therefore ask for registration.
Please register with this registration form.

Workshop Homepage: