Suche

zur Hauptseite

Peter Grünberg Institut
(leer)

Navigation und Service


Gate-all-around (GAA) Nanowire (NW)  MOSFETs

In order to increase current drive and better control short-channel effects (SCE), SOI MOSFETs have evolved from planar single gate to multi-gates, including double-, tri-gate FinFET and gate-all-around (GAA) NW FETs (Fig.1). The multi-gate structure provides a better electrostatic integrity that describes how well the gate controls the channel region. The electrostatic integrity is related to a “natural length” λ that can be derived from Poisson’s equation. The natural length represents the length of the channel region that is controlled by the drain. The SCE is suppressed if the gate length is larger than 5 to 10 times λ. λ decreases by increasing the number of gates (Table I).

Multigate MOSFET

Fig.1. Evolution of transistor from single gate SOI FET to GAA NW FET.

Table I: Natural length λ for different gate geometries

Tabelle Lambda

GAA Nanowire (NW) transistors  are particularly suitable designs for suppressing SCE. The all-around gate guarantees optimum electrostatics, as shown in Table I, and the one-dimensional quantum confinement effects reduce the carrier scattering. l can be scaled down further by reducing tSi and tox, and/or using high-K dielectric materials to increase eox.  Thin nanowires (<10nm) with high-k as the dielectric material are superior to GAA NW FETs.

We use e-beam lithography to fabricate nanowires with a diameter of <20nm, as shown in Fig.2 of an SEM image for free standing 20 nm strained Si NWs and NWs with a HfO2/TiN gate all around structure. Thinner NW can be achieved by oxidation and etching.

We are focusing on the following research topics:

  • ·         NW fabrication with a diameter of <10nm.
  • ·         High-k dielectric deposition on NW
  • ·         High mobility material NWs, like Si/Ge core-shell, strained-Si, and SiGe
  • ·         Low resistance contacts on NWs
  • ·         NW-FET with a gate length <20nm.


Gate all around Nanowire

 Fig.2. SEM images of a free standing 20 nm strained Si nanowire and NWs with HfO2/TiN gate all around (GAA).

Recent Publications

1. Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with
<100> and <110> channel orientations
Stefan Habicht, Sebastian Feste, Qing-Tai Zhao, Dan Buca, Siegfried Mantl
Thin Solid Films 520, pp.3332–3336, 2012
DOI: 10.1016/j.tsf.2011.08.034

2. Nanowire and Planar UTB SOI Schottky Barrier MOSFETs with Dopant Segregation
L. Knoll, A. Schäfer, S. Trellenkamp, K.K. Bourdelle, Q.T. Zhao and S. Mantl
Proc.13th International Conference on Ultimate Integration on Silicon (ULIS), pp.67-70, 2012

3. Strained Silicon Nanowire Array MOSFETs with High-k/Metal Gate Stack
S. Richter, S. Trellenkamp, M. Schmidt, A. Schäfer, K. K. Bourdelle, Q. T. Zhao, S. Mantl
Proc.13th International Conference onUltimate Integration on Silicon (ULIS), pp.75-78, 2012

4. Strained and unstrained silicon nanowire array MOSFETs: fabrication and physical analysis
Stefan Habicht
Ph.D thesis, RWTH Aachen, 2011
http://darwin.bth.rwth-aachen.de/opus3/volltexte/2011/3742/pdf/3742.pdf

5. Hole mobilities and electrical characteristics of W- gated silicon nanowire array FETs with <110> and <100> channel orientation
S. Habicht, S.F. Feste, Q.T. Zhao, and S. Mantl, 
Proceedings of 40th European Solid-State Devices Research Conference, 2010  pp.372-375


Servicemenü

Homepage