zur Hauptseite

Peter Grünberg Institut

Navigation und Service

Tunnel FET - Green Transistor

With the rapid increase of the number of circuits on a chip, power consumption has increased and appeared as the leading design challenge. State-of-the-art CMOS devices rely on a switching mechanism based on the modulation of thermionic emission from a thermally broadened Fermi function and are thus bound to a minimum inverse subthreshold swing of 60mV/dec at room temperature. This is a major obstacle for a further reduction of the operational voltage and hence the power consumption of integrated circuits.

An alternative nano-device structure is the Tunnel-FET (TFET), as is shown in the figure. Contrary to CMOS devices, a tunnel FET has an n+-i-p+ configuration and makes use of band-to band tunneling (BTBT) at the source/channel junction. The latter works like a band pass filter in which only high velocity carriers are capable of tunneling into the channel. These low-power devices (“green transistors”) promise inverse subthreshold swings far below the thermal limit of 60 mV/dec and very low off-state currents, enabling energy saving.

Nanowire-TFETStructure of a TFET on SOI substrate

TFET-NanowireFabricated Si nanowire array TFETs with n+ poly-Si gate. The Si nanowire has a cross section size of 20x20nm2

Selected Publications:

M. Schmidt, R. A. Minamisawa, S Richter, J.-M. Hartmann, R. Luptak, A. Tiedemann, D. Buca, Q. T. Zhao, S. Mantl,
Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors,
Proceedings of ULIS (Ultimate Integration on Silicon) 2011

C. Sandow.
Modeling, fabrication and characterization of Silicon tunnel field-effect transistors,
Ph.D thesis, Forschungszentrum Jülich 2010, ISBN 978-3-89336-675-0

C. Sandow, C. Urban, Q. T. Zhao and S. Mantl,
Silicon and Strained Silicon Nanowire Array Tunnel FETs
Proceedings of ULIS (Ultimate Integration on Silicon) 2010, pp.109-112

C. Sandow, J. Knoch, C. Urban, Q. T. Zhao and S. Mantl,
Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors,
Solid-State Electronics, 53 (2009) 10, pp. 1126 – 1129