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Tunnel FET - Green Transistor

With the rapid increase of the number of circuits on a chip, power consumption has increased and appeared as the leading design challenge. State-of-the-art CMOS devices rely on a switching mechanism based on the modulation of thermionic emission from a thermally broadened Fermi function and are thus bound to a minimum inverse subthreshold swing (SS) of 60mV/dec at room temperature. This is a major obstacle for a further reduction of the operational voltage and hence the power consumption of integrated circuits.
An alternative nano-device structure is the Tunnel-FET (TFET), as is shown in Figure 1 (left). Contrary to CMOS devices, a tunnel FET has an n+-i-p+ configuration and makes use of band-to band tunneling (BTBT) at the source/channel junction, providing SS far below the thermal limit of 60 mV/dec and very low off-state currents, and thus enabling much lower power consumption.
TFETs require low bandgap materials, steep tunneling junctions and improved electrostatics. However, low bandgap III-V and Ge TFETs are limited by the trap assisted tunneling (TAT) mostly caused by the poor quality of the high-k gate stacks. Pure Si TFETs are not very promising either, since the large indirect band gap limits the BTBT current. On the other hand, uniaxial tensile strained Si (sSi) nanowires (NWs) are promising since the shear strain along <110> direction lifts the degeneracy of the valence and conduction bands and causes a smaller band gap and furthermore, nanometer scaled wires inherently provide excellent electrostatic control of the device.
We developed a simple and novel method to fabricate very steep junctions by dopants implant into ultrathin epitaxial silicides. Dopant segregation by diffusion of dopants from the silicide to the silicde/sSi contacs at low temperature offers the advantage of creating self-aligned doped pockets with sharp dopant profiles and without typical ion implantation defects which give rise to TAT for the degradation of SS. On this base, we have fabricated nanowire n- and p-TFETs by tilted ion implantation using the high-k/TiN gate stack as implantation mask, as shown in Figure 1 (right) for a 10nm diameter NW TFET with a gate all around (GAA) structure.

Nanowire-TFETStructure of a TFET on SOI substrate

We have achieved very good sSi NW TFETs with:
• High on-currents: ION ~ 50 µA/µm at VDD = 0.5 V
• Very small point SS: 30mV/dec for n-TFET

We have reported the first sSi nanowire TFET inverter and NAND gate with:

• Very high gain (>24 at VDD=0.6V)
• Operation at very low VDD=0.2V
• First experimental verification of fast time response

Results were partly published in IEEE Electron Device Letters in June 2013 (DOI: 10.1109/LED.2013.2258652), and presented at IEDM 2013 and DRC 2014.

Selected Publications:

M. Schmidt, A. schäfer, R.A. Minamisawa, D. Buca, S. Trellenkamp, J.-M. Hartmann, Q. T. Zhao, S. Mantl,
„Line and point tunneling in scaled Si/SiGe heterostructure TFETs”,
IEEE ELECTRON DEVICE LETTERS VOL. 35, NO. 7, pp.699-701, 2014
DOI: 10.1109/LED.2014.2320273

Lars Knoll, Qing-Tai Zhao, Alexander Nichau, Stefan Trellenkamp, Simon Richter, Anna Schäfer, David Esseni, Luca Selmi, Konstantin K. Bourdelle, and Siegfried Mantl,
“Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors”
IEEE ELECTRON DEVICE LETTERS VOL. 34, NO. 6, pp.813-815, 2013
DOI: 10.1109/LED.2013.2258652

L. Knoll, M. Schmidt, Q.T. Zhao, S. Trellenkamp,A. Schäfer, K.K. Bourdelle, S. Mantl,
“Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions”
Solid-State Electronics, Volume 84, Pages 211–215, June 2013,
DOI: 10.1016/j.sse.2013.02.028

S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K. Bourdelle, Q. T. Zhao, and S. Mantl,
“Ω-Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs“
IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 11, pp.1535-1537, 2012
DOI: 10.1109/LED.2012.2213573

M. Schmidt, R. A. Minamisawa, S. Richter, A. Schaefer, D. Buca, J. M. Hartmann, Q. T. Zhao, and S. Mantl,
“Unipolar behavior of asymmetrically doped strained Si0.5Ge0.5 tunneling field-effect transistors”
APPLIED PHYSICS LETTERS 101, 123501 (2012)
DOI: 10.1063/1.4751356

Q.T. Zhao, W.J. Yu , B. Zhang, M. Schmidt, S. Richter, D. Buca, J.-M. Hartmann, R. Luptak,A. Fox, K.K. Bourdelle, S. Mant,
“Tunneling field-effect transistor with a strained Si channel and a Si0.5Ge0.5 source
Solid-State Electronics 74, pp. 97–101, 2012
DOI: 10.1016/j.sse.2012.04.018

M. Schmidt , R.A. Minamisawa, S. Richter, R. Luptak, J.-M. Hartmann, D. Buca, Q.T. Zhao, S. Mantl,
“Impact of strain and Ge concentration on the performance of planar SiGe band-to-band-tunneling transistors”
Solid-State Electronics 71, pp.42–47, 2012
DOI: 10.1016/j.sse.2011.10.018

Q.T. Zhao, J. M. Hartmann and S. Mantl,
“An Improved Si Tunnel Field Effect Transistor with a Buried Strained Si1-xGex Source”,
IEEE Electron Device Lett. 32, pp.1480-1482, 2011
DOI: 10.1109/LED.2011.2163696

Recent Conference Publications

Christian Schulte-Braucks, Simon Richter, Lars Knoll, Luca Selmi, Qing-Tai Zhao and Siegfried Mantl,
“Experimental Demonstration of Improved Analog Device Performance in GAA-NW-TFETs”,

Simon Richter, Christian Schulte-Braucks, Lars Knoll, Gia Vinh Luong, Anna Schäfer, Stefan Trellenkamp, Qing-Tai Zhao and Siegfried Mantl,
“Experimental Demonstration of Inverter and NAND Operation in p-TFET logic at Ultra-low Supply Voltages down to VDD = 0.15 V”,
Device Research Conference (DRC) 2014.

L. Knoll, Q.T. Zhao, A. Nichau, S. Richter, G.V. Luong, S. Trellenkamp, A. Schäfer, L. Selmi, K. K. Bourdelle, S. Mantl,
“Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling”,
International Electron Device Meeting (IEDM) 2013