Source-Drain Contact Engineering
For nanometer scale transistors reduction of source/drain (S/D) series resistance is most essential. The silicide layer used as the S/D contact should be thin and its contact resistance to the highly doped Si, SiGe or Ge should be very small. This holds, especially for devices fabricated on ultra thin SOI substrates. As the contact area is very small and the silicide layer is very thin, the contact resistance dominates the total S/D resistance. According to the International Technology Roadmap for Semiconductors (ITRS), for the 18nm technology node, the silicide layer thickness should not exceed 12nm and its specific contact resistivity on highly doped S/D should amount to 8×10-8Ohm cm2.
Ultra-thin silicides/germanides formed on Si, SiGe and Ge, which have a high thermal stability, low sheet resistance and low contact resistivity, and are uniform in morphology, are of our main interest