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Strained silicon on oxide (SSOI)

Strained silicon (sSi) permits a significant improvement of the electrons mobility, which created an enormous interest amongst designers of new nanoelectronic devices. At PGI-9 an approach was developed using He ion implantation and annealing for the relaxation of thin pseudomorph SiGe layers. This concept based on threading dislocation (TD) formation and movement, turned out to be competitive to the thick buffer concepts. Only thin buffers (<0.5 µm) are needed and the surface remains sufficiently flat (<5 Å) such that polishing is not required for wafer bonding. Although this concept was developed by a consortium of institutes within a German national program (TeSiN) and the Sinano network, the requirements for introduction into production line were achieved. The TD density could be lowered to ~105 cm-2 and the pile-up density to ~10 cm-1. GLOBALFOUNDERIES (formerly AMD Saxony) reported an 80% drive current improvement for long channel devices using these SSOI wafers and electron mobilities of 540 cm2/(V•s), much higher than 330 cm2 /Vs in non-strained SOI substrates.
The SSOI substrates are used for planar p, n-MOSFETS (link with Si NANOFETs) devices fabrication by integration with new high-k dielectrics and metal gates.

Strain fabricationThe "Jülich process" for the fabrication of strained silicon.

SSOI-TEMXTEM micrograph of a 60 nm sSi layer on an oxidized handling wafer. The inset shows the smooth interface between the single crystalline strained Si and the amorphous SiO2 layers. (M. Luysberg, PGI-5 and Ernst-Ruska Center)