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High mobility channel materials

In the past three decades, scaling of MOSFETs resulted in new technology generations every two to three years with doubled logic device density, lowered cost per logic function and increased chip performance. To continuously improve device performance, new device structures, new materials and strain engineering have been proposed and investigated. Among all these new technologies, strain engineering has been the dominant technique to enhance field-effect transistor performance during the past decade.

NMOS transistors processed on biaxial strained Si material show performance enhancements due to the mobility improvement of the carriers. The main drawback of biaxial stress is that at moderate strain states (~1GPa) only the electron mobility is increased. Hole mobility improvement requires high strain level or uniaxial strain type. However, several evidences indicate that the selection of optimal surface orientation leads to further enhancement of mobility. The highest reported hole mobility is for [110] channel p-MOSFETs on (110)Si and lowest on (001)Si material.
3D architectures, like nanowire-FETs or FinFETs, which involve transport on multiple surface orientations and assures an excellent electrostatic control, are also considered.
Intense research is performed, in particular for alternative high mobility channel materials. One major part is the investigation of novel MOSFET devices with Si/SiGe heterostructures or the even more challenging using strained Ge or GeSn materials.