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Semiconductor Nanowires

In the so-called bottom-up approach semiconductor nanostructures can be formed directly by epitaxial growth. In contrast to the alternative top-down method where lithographical means are used, this approach has the potential to simply the fabrication of low-dimensional semiconductor nanostructures enormously. Among the structures fabricated by the bottom-up approach semiconductor nanowires are particular interesting, since the one-dimensional channel can not only be used as a building block for future nanotransistor but also as a versatile basis for various quantum device structures.    More: Semiconductor Nanowires …


Molecular-beam epitaxy of topological insulator Bi2Te3 on Si (111) substrates

Recently a new state of matter called topological insulator (TI) has been theoretically predicted and experimentally observed in a number of materials [1]. Topological insulators are characterized by gapless surface states that show a linear energy dispersion, similar to relativistic particles. Hence, carriers at the surface of topological insulators have unparalleled properties, such as extremely high mobilities, or dissipationless spin-locked transport, and consequently these features may lead to new applications in the field of spintronics or quantum computing. More: Molecular-beam epitaxy of topological insulator Bi2Te3 on Si (111) substrates …


SiGe Quantum Cascade Lasers

Quantum cascade (QC) devices based on SiGe heterostructures are being studied to develop a Si-based laser in the mid-infrared spectral range. In QC lasers, the light is generated by intersubband optical transitions between the quantized states. Intersubband transitions are by nature direct, and hence a QC laser based on the indirect Si and Ge material systems is a conceivable avenue towards the realization of an efficient light emitter based on Si. More: SiGe Quantum Cascade Lasers …

Silicon field-effect-transistor

Alternative Gate Dielectrics

Many materials have been envisaged to replace SiO2 in a FET but the ideal candidate seems still not been found. Hf-based solutions might hold for the 45 nm node of the ITRS-roadmap but other materials are needed for further downscaling. We investigate ternary oxides (Rare Earth-Scandates) which are promising materials for this purpose. These materials are integrated in long channel MOSFETs and tested in other devices (e.g. ChemoFETs, nanowire-FET). More: Alternative Gate Dielectrics …

Strain fabrication

High mobility channel materials

In the past three decades, scaling of MOSFETs resulted in new technology generations every two to three years with doubled logic device density, lowered cost per logic function and increased chip performance. To continuously improve device performance, new device structures, new materials and strain engineering have been proposed and investigated. Among all these new technologies, strain engineering has been the dominant technique to enhance field-effect transistor performance during the past decade. More: High mobility channel materials …


Innovative Si(Ge)-based Nano Devices

Optimizations of Si-based nano-MOSFETs are required in order to increase the current drive and to suppress short-channel effects. The improvement of electrostatic integrity for a better gate control, lowering of source/drain series resistance, and enhancement of the carrier injection, are the main points of the study. The present research focuses mainly on the gate-all-around (GAA) nanowire MOSFET, Schottky barrier MOSFET and Tunnel FET-Green Transistor. More: Innovative Si(Ge)-based Nano Devices …


Novel 3-dimensional Ge dot crystals grown on templated Si substrates

Great attempts are being made to create new artificial materials for realizing prospective devices with novel functionalities. Templated self-assembly of quantum dots is regarded one possible avenue to realize such devices. Here we demonstrate an artificial 3-dimensional Ge quantum dot crystal hosted in a Si matrix, which is realized by means of templated self-assembly. More: Novel 3-dimensional Ge dot crystals grown on templated Si substrates …


The disposable DotFET:
Locally strained silicon for CMOS

The goal of the d-DotFET research activities is the evaluation of an entirely new path to fabricate strained Si nano-devices which are compatible to Si CMOS processing. The idea is to fabricate field effect transistors from strained Si bridges, which have been manufactured by disposing embedded, sacrificial Ge islands (dots). More: The disposable DotFET: Locally strained silicon for CMOS …