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Peter Grünberg Institute
Semiconductor Nanoelectronics (PGI-9)
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George Smith Award Qing-Tai Zao 2019
George Smith Award
At IEDM in San Francisco on Dec. 3rd, 2018, IEEE Electron Device Society (EDS) presented the George E. Smith Award to the scientists from PGI 9 and EPFL, Switzerland, for their paper entitled “Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study”, which was published in the IEEE Electron Device Letters in October 2017 (DOI: /10.1109/LED.2017.2734943). Dr. Gia V. Luong, Prof. Qing-Tai Zhao and Prof. Siegfried Mantl from PGI 9, share the award equally with the colleagues from EPFL. Advanced silicon nanowire devices were reported in this paper for the future energy efficient nanoelectronics.
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InAs-Nanowire

Research Topic

Semiconductor nanowires can be formed directly by using the so-called bottom-up approach. In contrast to the usual top-down method where optical or electron beam lithography is employed, this approach has the potential to simply the fabrication of low-dimensional semiconductor nanostructures enormously. More: Research Topic …

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What alternatives are there to present computers based on crystals of silicon or other semiconductors? What is – from a physical point of view – the smallest possible device that can be used to perform computational processes? Is there a minimum amount of energy required for floating point operations?
JARA

Three students attending the JARA FIT labcourse dressed in a cleanroom overall

JARA FIT Lab Course

Students are invited to participate in the JARA-FIT Lab Course Nanoelectronics. The goal of the practical course is to advance students to current research topics from nano-electronics. Therefore selected experiments take place at genuine research equipments. More: JARA FIT Lab Course …


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