Navigation and service

QPACE

QPACE was deployed mid 2009 with four racks each at the Research Center Jülich and at the University of Wuppertal. It is being used for the simulation of fundamental forces in elementary particle physics, especially in the research area of quantum chromodynamics (QCD). QCD describes, for example, how a proton is made up out of quarks and gluons. QPACE is being used by members of the Collaborative Research Center/ Transregio 55 "Hadron Physics from Lattice QCD," which is located at the Universities of Regensburg and Wuppertal and supported by the German Research Foundation (DFG).

QPACE

The heart of QPACE is the IBM PowerXCell 8i processor, an enhancement of the Cell/B.E. processor, which originally was developed by Sony, Toshiba and IBM for the Sony PlayStation 3. With its nine processor cores, the chip can carry out a very large number of calculations simultaneously and at a high speed. The novel concept of QPACE consists of connecting processors by a network of programmable units, called Field Programmable Gate Arrays (FPGA), to an efficient scalable computer. Each of the QPACE installations in Jülich and Wuppertal can reach a maximum performance of 100 TeraFlops (double precision). That equates to 100 trillion (100,000,000,000,000) computing operations per second. As a result of the scalability of the network, it is in principle possible to increase the performance to the PetaFlops scale (one quadrillion operations per second). The technology concepts developed for the QPACE project are setting the trend for future high-performance computers. One example of this is the new cooling concept developed in the IBM research and development center in Böblingen, which can contribute significantly to the energy efficiency of future supercomputer installation.

QPACEQPACE
Copyright: Forschungszentrum Jülich

The DFG as well as the states of Bavaria and North Rhine Westphalia are bearing the costs of QPACE in the amount of approximately three million euros. The consortium and IBM are dividing the development costs between themselves. Additional subsidies within the framework of the eQPACE project of the European research initiative PRACE (Partnership for Advanced Computing in Europe) serve to develop a more general communications structure for the FPGA network and thereby to open QPACE to a wider range of applications.

Technical data of QPACE:

Type: massively parallel supercomputer
Performance: 26 TeraFlops per rack (double precision)
Processors: 256 per rack
Processor type: PowerXCell 8i
Primary storage: 1 Terabyte per rack
Racks: 8 (4 in Jülich, 4 in Wuppertal)
Network latency: 3 microseconds
Network bandwidth: 6 Gigabyte/s per node
Power consumption: ca. 30 kilowatts per rack