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HPC Optimization and Scaling Workshop

(Course no. 1292019 in the training programme 2019 of Forschungszentrum Jülich)

18 Feb 2019 09:00
22 Feb 2019 17:00
Jülich Supercomputing Centre, Rotunda, building 16.4, room 301
Target audience:
Users of the supercomputers in Jülich

This course will give users of JSC's supercomputing systems hands-on practical training with a variety of tools available to assist with performance analysis, optimisation and scaling of HPC applications on Intel architectures, to help make efficient use of allocated resources on JUWELS (Skylake) and JURECA (Haswell & KnightsLanding). Participants are encouraged to prepare representative small/short-running application test-cases convenient for experimentation in the hands-on sessions with expert coaching.

Note that assistance for porting, building and running applications will not be available during the workshop, but can be requested in advance.

Topics covered include:

  • Structured parallel performance engineering
  • Execution characterisation and MPI correctness validation
  • Single-core performance analysis including vectorisation
  • Multi-threading and node-level/roof-line analysis
  • Multi-node performance/scalability analysis

Participants should bring their own notebooks.


Participants should belong to a currently active compute project on our systems (project-ID!) and should already have an active user account (user-id!). Test runs during the workshop will be done on the participants' own project accounts.

In order to gain maximum benefit from this workshop, participants should have an in-depth (hands-on) knowledge of the algorithms and codes used in their project.

In addition, we also ask participants to prepare a test case to evaluate the initial performance of their code and to monitor the progress.

 Agenda for the HPC Optimisation and Scaling Workshop (PDF, 54 kB)
This course is given in English.
5 days
18-22 February 2019, 09:00-17:00
Jülich Supercomputing Centre, Rotunda, building 16.4, room 301
Number of participants:
maximum 25
Intel representatives, JSC staff members
via the registration form
Further information:
see Workshop Homepage