The BMBF-funded NEUROTEC project is at the forefront of advancing high-tech capabilities and fostering structural transformation in the digitalization sector. It focuses on the development of innovative neuromorphic electronic hardware and accompanying software, with the memristive cell as its core technology, utilizing various physical memory mechanisms. Through a combination of fundamental research and the creation of demonstrators, the project collaborates closely with industry partners in the Rhineland region, driving technological progress and industrial innovation.Together with its sister project NeuroSys thriving economic ecosystem for neuromorphic AI hardware and software in the Aachen-Jülich region is envisaged.
The Demonstrator Project (DP) work package focuses on developing systems, circuits, and technologies to gain in-depth insights into memristor integration, control, and operation, with the goal of creating commercially viable, technology-transferable solutions.
D0
Under the first of the DP called D0, various standalone memristor types and fundamental memristor array units of new computing paradigms like Compute-In-Memory, (CIM), Content-Addressable-memory (CAM) are developed and their integration with commercial foundry wafers (300mm) are researched.
D1
Taking the insights from D0, the fundamental units are then converted into computing elements and array of computing elements to address state of art computing bottlenecks. While D0 aimed only for the electrical characterization, D1 involves complex analog – mixed and digital hardware to enable the communication to the outside work, integration with external high-end processor architectures and accelerators and complex network on chip to test advanced computing paradigms.
D2
Architectures from D1 are tuned for user end applications catering for various algorithms hence creating a end-end computing solution in D2
Tapedout Chips under NEUROTEC II
D0
Dolphin-DAD
Dolphin-COOP
D0
Dolphin DAD
Dolphin- COOP
6x6 mm 28nm CMOS Chip
Integrated CMOS structures for 1T1R, 2T1R memristor units
Integrated Content Addressable Memory units and arrays
Integrated Compute in Memory unit and arrays
VCM and PCM mode memristor units
1.4 x 1 mm 28nm CMOS Chip in QFN 40
Integrated Memristor Control circuit HRS, LRS and read for 2 x 2 arrays
Current mode SAR ADC with adaptive Dynamic range
Integrated RISC-V and memory for error correction and control
1.4 x 1 mm 28nm CMOS Chip in QFN 40
7 coupled PLLs for Oscillatory Neural Network
Analog and multilevel phase coupling
Scalable ONN with all to all and multi cluster coupling