Neethu Kuriakose - DR project

Application of memristors in standard IC building blocks

Doctoral Researcher: Neethu Kuriakose
Local ZEA-2 Supervisor: Ashok Arun
Academic Supervisor: Stefan van Waasen, University of Duisburg-Essen (UDE)
Topic: Neuromorphic Computing
Research Field: Information

Fig 1. Schematic of 1T1M integration. a) Cross-section of a Memristor integrated on a CMOS chip. NMOS fabrication up to Via 4 (V4) is carried out in a foundry with 250 nm technology. Ta/TaOx/Pt thin film stack is integrated aligning to V4 by lab Memristor BEOL process. b) SEM image of a pair crossbar TE and BE from top view. c) A cross-section TEM image of Memristor showing the stack of materials and thickness.[1]

As the so-called Moore's law faces fundamentally physical challenges, new computational approaches are in demand to slow down or even reduce worldwide information processing energy consumption in the future and allow for further scaling. More than Moore approaches try to tackle the physical limitations of Moore’s law by implementing application driven components, which are rarely used in modern CMOS processes.

Elementary Memristor is a two terminal “Memory Resistor”, which offers fast, non-volatile, low energy electrical switching. In1971, Leon Chua introduced the concept of Memristors as a missing fundamental element in electronics.

Fig 2. Memristor Conductance Control Architecture

Memristors are gaining attention to the scientific community due to its properties like Atomic structure, Energy efficiency, Scalability, in memory computation and compatibility with CMOS Technology, and is much studied in the field of Neuromorphic computing.

However, CMOS based control circuitry for controlling Memristor analog conductance is still under scientific investigations. This work focusses on energy efficient control circuitry based on voltage control mode as well as current control mode, a comparative study of both the techniques and development of a computing architecture inTSMC28nm technology. Later on applications including vector – matrix multiplication, image/speech processing, cryptography could be tested.

Modification to the above CMOS-MEMRISTOR architecture is done (Fig 2) to get conductance control for ReRAM based Memristor, in such a way that it could be used for future neuromorphic based applications.


[1] Low conductance and multilevel CMOS – Integrated Nanoscale Oxide Memristors; Xia Sheng, Catherine E Graves, Suhas Kumar, Xuema Li, Brent Buchanan, Le Zheng, Sity Lam, Can Li and John Paul Strachen
[2] Variability-Aware Modeling of Filamentary Oxide-Based Bipolar Resistive Switching Cells Using SPICE Level Compact Models- C. Bengel, A. Siemon, F. Cüppers, S. Hoffmann-Eifert, A. Hardtdegen, M. von Witzleben, L. Hellmich, R. Waser and S. Menzel, IEEE Trancsactions on Circuits and Systems-I, VOL. 67, NO. 12, 2020.
[3] 50x Endurance Improvement in TaOx RRAM by Extrinsic Doping – 2021 IEEE International Memory Workshop-Tim Kempen, Rainer Waser, Vikas Rana

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Last Modified: 15.08.2023