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Digital circuit design and system modeling of signal chain of a neutrino detector

Pavithra Muralidharan is a PhD student working in IC design at ZEA-2. The prime focus of her PhD thesis is on digital circuit design and system modeling of receiver chain of a neutrino detector. The detector uses photomultiplier tubes (PMTs) to convert photons, which are generated by the incident neutrinos into a signal current. A read out circuit converts the current signal into a voltage and subsequently to digital data. Fluctuations in the biasing of the PMT creates an offset in the baseline of the generated signal. This offset alters the charge measurement results of the readout. A regulation loop to counteract this effect and is included in the readout circuit of the detectors. Another undesirable outcome caused by the high voltage cables is the overshoot of large signals in the PMTs. An overshoot compensation unit will serve to improve the quality of the signal being measured. The goal of Pavithra’s thesis is to model the receiver chain and to design control loops for offset and overshoot compensations of signals from the PMTs. In addition, she is responsible for the design of a data processing unit designed to reduce the data rate and perform noise compression for further data reduction.

Block diagram of the Vulcan chipBlock diagram of the Vulcan chip, blocks involved in the research topic are highlighted in red
Copyright: Forschungszentrum Jülich GmbH

Publications by Pavithra Muralidharan: