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Innovative Si(Ge)-based Nano Devices

Optimizations of Si-based nano-MOSFETs are required in order to increase the current drive at low voltage and to suppress the short-channel effects. Improvement of electrostatic integrity for a better gate control, lowering of source/drain series resistance, and enhancement of the carrier mobility and injection are the main points of study. Novel device structures, like gate all around nanowire MOSFET, will be investigated. The device performance will be optimized by channel engineering with high mobility materials, gate engineering with high-k or higher-k dielectric and metal gate for improved electrostatics, source/drain engineering for low resistivity contacts on steep and shallow junctions.

Another very important issue for the future nano-device concept is to reduce the power consumption for energy saving. New device structures beyond CMOS will be studied. Steep slope band-to-band Tunneling FET (TFET) is a promising device structure for ultra-low power applications. At present we focus on gate all around nanowire TFETs and logic circuits.

All those novel device structures will be combined with our research of the new materials, like strained-Si, SiGe, Ge/GeSn, SiGeSn and core-shell structures, and alternative high-k dielectric materials, to improve their performance.