Muhammad Uzair Talal Chishti - DR project
Network-on-chip based computing architecture for numerous Neuromorphic accelerators
Doctoral Researcher: Muhammad Uzair Talal Chishti
Local ZEA-2 Supervisor: André Zambanini
Academic Supervisor: Stefan van Waasen, University of Duisburg-Essen (UDE)
Topic: Neuromorphic Computing
Research Field: Information
As the world is advancing, so are our computers. While modern computers can now accomplish many dauntless and complex tasks, they still lack in few key aspects.
In-addition to high power demands, there is a bottleneck associated with the von Neumann architecture (separate memory and computing location). Hence, there is a greater need for a new computing paradigm that address these points.
The mammal brain makes an interesting case to address these problems. The brain, as the inspiration for neuromorphic systems, does not possess a von Neumann bottleneck due to the tight locality between data and computing and thus consumes energy in fraction of even supercomputers.
Here in Jülich, we are developing such neuromorphic circuits from scratch. From concept to design, from hardware description to tapeout. Additionally, in order to connect these neuromorphic circuits with more Moore and beyond Moore systems, there is a necessity for an advanced interconnect methodology that complements the neuromorphic computing challenges. Traditional bus-based architecture have massive limitation even for today’s computer architecture.
One such solution for the interconnection is a network-on-chip (NoC). NoCs provide massive parallelism and scalability for the neuromorphic circuits, along with high gain in area, throughput, latency, bandwidth and above all, power consumption.
Under the project umbrella of NEUROTEC-II, this doctoral research focuses on the design and development of such complex NoCs to provide efficient and state-of-the-art communication technique for different memristor based neuromorphic tiles.