Tapeout for an ADC Prototype Chip Completed
The chip design of a configurable ADC has been successfully send to the manufacturer at the end of May. This final step towards the realization of an integrated circuit in silicon is called a tapeout and is always quite the milestone. In this case, roughly 7500 hours of work accumulated in a building plan, the so-called layout, and with a digital gate count of more than 330 000 – all squeezed in a one by one millimeter area with nanometer feature sizes. After the chip design is finished, a four to five months production phase is initiated.
The New Generation ADC 28nm project is mainly driven by our doctoral researcher Lukas Krystofiak to identify an ADC architecture in a 28nm CMOS process that is flexible and power efficient to enable the use in various applications, especially for particle detector readouts. This ADC features a 10 bit digitizer that scales well with power consumption when reducing the sampling speed and a configurable frontend that adapts with its impedance to the sensor in question. The demonstrator is completed with integrated and automated data reduction techniques to reduce the required transmission bandwidth and up to six high-speed output drivers.
Of course, not everything in this project and especially the design work is done by Lukas himself. He got support by many experienced colleagues of the IC Development team. Altogether, they ensured with the best of their knowledge a proper design that obeyed all requirements in simulations. However, simulations on a PC are all good and fine, the final piece of silicon in the lab will show the strengths and weaknesses. As always, it will be thrilling moment to power up the chip and observe if all of the many gears in this tiny machine work as intended and bring it to life.