
Laufzeit
March 2025 bis February 2028
Kontakt
Dr. Andreas Herten
Co-Lead of division Novel System Architecture design, head of ATML Accelerating Devices PI in Helmholtz Information Program 1, Topics 1 and 2
Gebäude 16.3 / Raum 228
+49 2461/61-1825
E-MailDARE (SGA1)
HPC Digital Automony with RISC-V in Europe
DARE SGA1 sets out to build a fully European supercomputing stack for HPC and AI, featuring high-performance and energy-efficient processors designed and developed in Europe and an integrated, high-performing software stack. The initiative is a direct response to Europe’s strategic need for digital sovereignty, ensuring that the continent has full control over its critical computing infrastructure.
The project, HPC Digital Autonomy with RISC-V in Europe or DARE, will take advantage of these technology trends, build on the current European RISC-V HPC research foundation (EPI, EUPILOT, eProcessor, and MEEP), as well as the results from previous Arm HPC initiatives originated from the Montblanc projects (EUPEX) and other related projects (e.g. DEEP-SEA), and add direct technology exploitation paths to create European HPC products for European supercomputers for research and industry. DARE proposes to build prototype HPC and AI systems based on EU designed and developed, industry-standard chiplets using the latest silicon technology nodes to meet the highest performance and energy efficiency requirements. DARE will adopt a co-design approach to guide the full stack and related infrastructure research and development to enable European Digital Autonomy in the HPC and AI domains.
DARE will be guided by leading HPC centres with their expert knowledge of critical HPC and AI applications across various domains. The centres will help define the key requirements and Key Performance Indicators (KPIs), shaping the design and development of DARE’s hardware and software systems. Furthermore, these centres will integrate prototypes into pre-operational environments, which will leverage the outcomes from DARE Phase 2 towards the post-Exascale production HPC and AI systems in Phase 3 and beyond.