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New concepts for digitalized frequency synthesizers in CMOS

Motivation and introduction:
In large scale particle detectors the requirements on the signal receivers are getting more complex. To meet this, the receivers have to be complex integrated circuits, which do not only integrate the analog part of the receiver, but as well the mixed signal and digital processing. More and more of the functionality of a single receiver is implemented locally in the receiver. In this way the data transfer in the detector can be reduced.
On chip frequency synthesis is required for time measurements of signals and as a clock for the digitalization of the signal. In order to keep the quantization error small, the requirements of the frequency synthesis have to be full filled. A fully integrated Phase Locked Loop (PLL) is used for the frequency synthesis to reduce pin count and costs. While the concepts of PLL in general are well investigated, a more digitalized approach will be needed, with the goal to decrease both the die size and the power consumption of the receiver. A digitalized approach ensures also that the PLL can be reused as a building block, since the performance and parameters can be programmed to meet the requirements of new receivers.
Following, the block diagram of fractional PLL with its sub- circuits is shown. PLL receives a low frequency signal at the input and using a feedback structure, generates a much higher frequency at the output which is synchronized in phase and frequency with reference clock. The output clock should realize minimum jitter requirements to reduce the clock uncertainty effects when it is used as sampling clock in ADC and digital parts.

Phase locked loop block diagramPhase locked loop block diagram
Copyright: Forschungszentrum Jülich GmbH


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