Trainingskurs "Node-Level Performance Engineering"

28.04.2016 07:00 Uhr
29.04.2016 15:00 Uhr
Jülich Supercomputing Centre, Rotunda, Geb. 16.4, R. 301

(Kurs-Nr. 218/2016 im Trainingsprogramm des Forschungszentrums)


Nutzer der Supercomputer in Jülich




Grundkenntnisse in den Programmiersprachen C, C++ oder Fortran


Der Kurs wird auf Englisch gehalten.


28-29 April 2016, 9.00-17.00 Uhr


Jülich Supercomputing Centre, Rotunde, Geb. 16.4, R. 301

Anzahl Teilnehmer:

maximal 60


Dr. habil. Georg Hager, Prof. Dr. Gerhard Wellein, RRZE/HPC, Universität Erlangen

Ansprechpartner im JSC:

Christian Feld

This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit of optimizations can often be predicted. We introduce a "holistic" node-level performance engineering strategy, apply it to different algorithms from computational science, and also show how an awareness of the performance features of an application may lead to notable reductions in power consumption.

  • Introduction and Motivation
  • Performance Engineering as a process
  • Topology and affinity in muticore systems
  • Microbenchmarking for architectural exploration
  • Beyond Roofline: The ECM Model
  • Optional: Energy-efficient code execution

The Roofline Model

  • Basics and simple applications
  • Case study: sparse matrix-vector multiplication
  • Case study: Jacobi smoother

Model-guided optimization

  • Blocking optimization for the Jacobi smoother

Programming for optimal use of parallel resources

  • Single Instruction Multiple Data (SIMD)
  • Cache-coherent Non-Uniform Memory Architecture (ccNUMA)
  • Simultaneous Multi-Threading (SMT)

Pattern-guided performance engineering

  • Hardware performance metrics
  • Typical performance patterns in scientific computing
  • Examples and best practices
Letzte Änderung: 11.04.2022