Training for Maxeler Dataflow Architectures
In the context of the PRACE-3IP Pre-Commercial Procurement (PCP) project, Maxeler ported a set of scientific computing applications to its FPGA-accelerated architecture and deployed a pilot system at Jülich Supercomputing Centre.
Developers of numerical applications with general interest in exploring the use of FPGAs for accelerating applications are invited to participate in this training event. No previous background in FPGA programming is required.
Lecturers will be leading experts from Maxeler. All participants will be provided with access to the Maxeler pilot system JUMAX.
The training will start on 20.9.2018, 9am and end at 21.9.2018 at 2pm.
The number of participants is limited to 30 people.
Agenda:
Thursday, 20 Sept. 2018
Time | Topic |
|---|---|
09:00 - 10:15 | Session 1: 09:00: Welcome and Introductions 09:15: Introduction to Dataflow, Using Maxeler Dataflow Engines (SLiC) |
10:15 - 10:30 | Coffee |
10:30 - 12:30 | Session 2: 10:30: Programming Data Flow Engines, Loops and Arithmetic in Space 11:30: Modelling and Optimising Data Flow Engines |
12:30 - 13:30 | Lunch |
13:30 - 15:00 | Session 3: Excercises I |
15:00 - 15:30 | Coffee |
16:00 - 17:30 | Session 4: Excercises II |
18:30 - 21:00 | Dinner (Restaurant El Toro, Jülich) |
Friday, 21 Sept. 2018
Time | Topic |
|---|---|
09:00 - 10:00 | Session 5: DFE System Optimisations Deep Dive with LoopFlow Graphs |
10:00 - 10:15 | Coffee |
10:15 - 12:15 | Session 6: 10:15: Elementary Functions on DFEs 11:15: Porting Existing Applications to Data Flow Engines |
12:15 - 13:30 | Lunch |
13:30 - 14:30 | Session 7: Excercises III |
14:30 - 14:45 | Coffee |
14:45 - 16:30 | Session 4: Excercises IV (optional) |