IAS Seminar: The EPI vector RISC-V accelerator: architecture, platform, tools and hands-on

Start
25th April 2023 12:00 PM
End
25th April 2023 03:00 PM
Location
JSC, Rotunda, building 16.4, room 301, and online via Zoom

Speaker

Dr. Filippo Mantovani, Barcelona Supercomputing Centre, Spain

Date

Tuesday 25 April 2023,
Presentation: 14:00-15:00 (open to everyone, on-site and online)
Hands-On session: 15:00-17:00  (limited amount of participants, only on-site, see details for registration below)

Venue

On-site: JSC, Rotunda, building 16.4, room 301.
Online via Zoom: https://fz-juelich-de.zoom.us/j/99566055524?pwd=RkhScGNKV1h6WklGRWxteVhJcjNtUT09

Abstract Talk (14:00-15:00)

The European Processor Initiative (EPI) is a project aiming to develop a general-purpose processor and an accelerator as well as the software layers needed for their adoption by the HPC community. The Barcelona Supercomputing Center is promoting and participating in developing of the RISC-V-based accelerator targeting HPC. The first part of the seminar will provide an overview of the EPI project with particular attention to the co-design effort performed with Software Development Vehicles (SDV) while developing the EPI accelerator leveraging the RISC-V vector extension. The second part will be dedicated to a demo/hands-on experience on the RISC-V platforms hosted at BSC: test accounts will be provided to the attendees and participants are invited to bring their scientific codes to test.

Slides and Video

Title

Note

Link

Publication Date

The EPI vector RISC-V accelerator: Architecture, platform, tools and hands-on

Slides of the talk "The EPI vector RISC-V accelerator" in the IAS Seminar on 25 April 2023
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26th April 2023

Hands-On (15:00-17:00)

A limited amount of participants (maximum 15 different codes) can bring a code and test it via remote access on the RISC-V software development vehicle (SDV). Participants must be on-site at JSC and have to register beforehand.

Constraints: you need an app (mini-app, kernel or scientific code) that can run stand-alone on a single core with potential for vectorization.

Some hints on the code that could make the hands-on more productive:

  •     Application written in C/C++ or FORTRAN language
  •     Possibility to run a use case of the application as a sequential program
  •     We will not focus on MPI/OpenMP, but we could provide some support
  •     No strong dependencies with CUDA/OpenACC
  •     Avoid "complex" dependencies (to avoid having to recompile tons of libraries)
  •     Avoid heavy I/O traffic

In case of doubt or questions, please contact Estela Suarez (email see below)

Registration for hands-on: send an email before 17 April 2023 to Estela Suarez (e.suarez@fz-juelich.de).

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Last Modified: 20.06.2023