JURECA Booster Installation Finalized

Since the announcement of the partnership between JSC, Intel, Dell and ParTec for the deployment of a Booster module for the JURECA system (see JSC News No. 250), the partners - together with the JURECA Cluster module supplier T-Platforms - have been working on installing the system and integrating it with the existing infrastructure. The Booster extends the 1,884-node Cluster with 1,640 additional compute nodes, featuring an Intel Xeon Phi 7250-F (Knights Landing) processor with 96 GiB main memory, interconnected by an Intel Omni-Path Architecture network. JSC and Intel designed the Booster component to complement the Cluster with an architecture focused on capability computing. The Booster is installed in 33 racks side-by-side with the 34 racks of the Cluster system in the JSC facility and shares the same administrative infrastructure, including the login partition. Both systems are high-speed interconnected through 198 bridge nodes.

Following the preparation of the facility until the end of August, the installation of the Booster equipment took place in September and October. In late October, JURECA was temporarily taken offline to finalize the integration and stabilization of the whole system. Following system acceptance in November, JSC expects to make the full Booster component available to users at the end of the month. The necessary system software extensions to enable cross-module job scheduling and execution are currently available at prototype and release-candidate level and are expected to be generally available in early 2018.

Computing time on the JURECA Booster will be made available to members of Forschungszentrum Jülich and RWTH Aachen University through JARA-HPC/VSR calls. Moreover, during an interim period, scientists at German universities and research institutions can request computing time via the John von Neumann Institute for Computing (NIC) calls.
(Contact: Dr. Dorian Krause, d.krause@fz-juelich.de)

JSC News No. 253, 30 November 2017