The European Processor Initiative (EPI) is a research project whose aim is to design and implement a roadmap for a new family of European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications.

The EPI project is structured in various streams:

• Stream 1 will bring up EPI’s first generation processor (Rhea-1) and board, then connect the EPI accelerator (EPAC-v1.0/v1.5) to the board via PCIe to build a hardware prototype on which software will be installed and applications ported. This will serve to validate the first generation of European processors targeted for the HPC market. Simultaneously, a co-design process will take place targeting the second EPI generations (Rhea-2 and EPAC v2) chips to be developed in EPI. Application requirements will be collected and simulation-based architecture analysis performed to identify the best suited design parameters.

• Stream 2: develops the general purpose processor Rhea, targeting future European exascale supercomputers. The design is based on Arm V1 cores, HBM, DDR5, PCIeG5/CXL/CCIX. This stream also develops an open Common Platform aiming to efficiently interface processors and accelerators in-package, implementing cache coherency, and validating the toolchains and runtime between processors and accelerators.

• Stream 3: develops the EPAC accelerator processor using fully European IPs based on the RISC-V Instruction Set Architecture (ISA). The EPAC architecture includes RISC-V vector tiles (VTILE), specialized Deep Learning and Stencil accelerators (STX), and variable floating point precision cores (VRP) all carefully engineered in a heterogeneous tile architecture whose subunits comply to the RISC-V standardization efforts.

JSC contribution: The JSC leads Stream 1 and contributes to the validation of the first generation Rhea and EPAC, and to the codesign of their future generations. In particular, JSC develops a gem5 simulation package for the Arm-based Rhea, which enables quantitatively evaluating the impact of different chip designs into the performance and energy efficiency seen by benchmarks and applications.