On the way to a next-generation modular supercomputer

Jülich, 28 April 2017 – Intel and Forschungszentrum Jülich together with ParTec and DELL today announced a cooperation to develop and deploy a next-generation modular supercomputing system. Leveraging the experience and results gained in the EU-funded DEEP and DEEP-ER projects, in which three of the partners have been strongly engaged, the group will develop the necessary mechanisms required to augment JSC’s JURECA cluster with a highly-scalable component named “Booster” and being based on Intel® Scalable Systems Framework (Intel® SSF).

“This will be the first-ever demonstration in a production environment of the Cluster-Booster concept, pioneered in DEEP and DEEP-ER at prototype-level, and a considerable step towards the implementation of JSC’s modular supercomputing concept”, explains Prof. Thomas Lippert, Director of the Jülich Supercomputing Centre. Modular supercomputing is a new paradigm directly reflecting the diversity of execution characteristics, found in modern simulation codes, in the architecture of the supercomputer. Instead of a homogeneous design, different modules with distinct hardware characteristics are exposed via a homogeneous global software layer that enables optimal resource assignment.

Code parts of a simulation that can only be parallelized up to a limited concurrency level stay on the Cluster – equipped with faster general-purpose processor cores – while the highly parallelizable parts are to run on the weaker Booster cores but at much higher concurrency. In this way increased scalability and significantly higher efficiency with lower energy consumption can be reached, addressing both big data analytics and Exascale simulation capabilities.

“Intel’s holistic solution portfolio for high performance computing democratizes access to powerful tools for scientific discovery and commercial innovation," said Trish Damkroger, Vice President of Technical Computing at Intel. “As we look to the challenges of improving performance and system efficiency, advances like JSC’s modular supercomputer concept will help bring ever greater capabilities to more users, to extend what is possible with HPC clusters.”

Technical Specifications

The JURECA Booster will use Intel® Xeon Phitm processor 7250-F with on-package Intel® Omni-Path Architecture (Intel® OPA) interfaces for maximum scalability and power efficiency. The system will be delivered by Intel with its subcontractor Dell, utilizing Dell’s PowerEdge C6230P servers. Once installed, it will provide a peak performance of 5 Petaflop/s. The system was co-designed by Intel and JSC to enable maximum scalability for large-scale simulations. The JURECA Booster will be directly connected to the JURECA cluster, a system delivered by T-Platforms in 2015, and both modules will be operated as a single system. As part of the project a novel high-speed bridging mechanism between JURECA’s InfiniBand EDR and the Boosters’ Intel OPA interconnect will be developed by the group. Together with the modularity features of ParTec’s ParaStation ClusterSuite, this will enable efficient usage of the whole system by applications flexibly distributed across the modules.

Superrechner JURECA
Superrechner JURECA am Jülich Supercomputing Centre (JSC)
Forschungszentrum Jülich / Ralf-Uwe Limbach

Further information

Press release, 5 November 2015: „Supercomputer with turbocharger“
Projekt-Website DEEP
Projekt-Website DEEP-ER
Jülich Supercomputing Centre (JSC)


Prof. Dr. Dr. Thomas Lippert
Head of Jülich Supercomputing Centre (JSC)
phone +49 2461 61-6402
e-mail th.lippert@fz-juelich.de

Dr. Dorian Krause
Jülich Supercomputing Centre (JSC)
phone +49 2461 61-3631
e-mail d.krause@fz-juelich.de

Press contact:

Tobias Schlößer, press officer
Forschungszentrum Jülich
phone +49 2461 61-4771
e-mail t.schloesser@fz-juelich.de

Last Modified: 22.05.2022